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| ? 2011 nuvoton technology corporation www.nuvoton.com NPCT42X trusted pl atform module (tpm) preliminary march 2011 revision 1.1 NPCT42X trusted pla tform module (tpm) general description the NPCT42X single-chip trusted platform module (tpm) is a family of third-generation, nuvoton safekeeper ? technolo- gy devices. the devices impl ement the trusted computing group (tcg) version 1.2 specif ications for pc-client tpm. the NPCT42X devices are desi gned to reduce system boot time and trusted os loading ti me. they provide a solution for pc security for a wide range of pc applications. the NPCT42X family of devices are microsoft ? windows ? compliant and are supported by linux kernel v2.6.18 and higher. features general single-chip tpm solution ? no external parts required compatible with tpm main specification version 1.2 revision 116 and pc client specific tpm interface specification version 1.21 revision 72 host interface ? tpm 1.2 standard interface (tis) with five localities ? supports legacy locality by using tis protocol with i/o mapped registers secure general-purpose i/o (gpio) ? five gpio pins ? i/o pins individually configured as input or output ? configurable internal pull-up resistors ? tcg 1.2-defined interface ? dedicated physical presence (pp) pin with config- urable pull-up or pull-down resistor tick counter bus interface lpc bus interface ? based on intel?s lpc interface specification revi- sion 1.1, august 2002 ? tpm 1.2 interface (tis) clocking and supply on-chip clock generator power supply ? 3.3v supply operation ? separate pins for main (v dd ) and standby (v sb ) power supplies ? low standby power consumption software tpm bios drivers: memory absent (ma) and memory present (mp) tpm device driver for microsoft windows ntru cryptosystems (acquired by security innova- tion ? ) core tcg software stack (ctss) wave systems cryptographic service provider (csp) with either embassy ? security center (esc) or embassy trust suite (ets) oem edition chipset superi/o lpc bus physical presence gpio system block diagram NPCT42X free datasheet http://
features (continued) www.nuvoton.com 2 revision 1.1 NPCT42X product-specific information the following table lists the available products in the NPCT42X family. software NPCT42Xa NPCT42Xb NPCT42Xc NPCT42Xd 1 1. restricted availability; please contact your nearest nuvoton office. see back cover for details. NPCT42Xl tpm bios drivers ? ???? ntru cryptosystems ctss ??? wave systems csp and esc ?? wave systems ets oem edition ? free datasheet http:// 3 www.nuvoton.com revision 1.1 NPCT42X datasheet revision record revision date status comments march 2011 revision 1.0 preliminary NPCT42X datasheet. may 2011 revision 1.1 NPCT42Xl added. free datasheet http:// www.nuvoton.com 4 revision 1.1 NPCT42X table of contents features.............................................................................................................................................................. 1 product-specific information................................................................................................... ............................ 2 datasheet revision record ............................................................................................................................... 3 1.0 signal/pin connecti on and description 1.1 connection diagram ......................................................................................................... .. 6 1.2 buffer types and signal/pin directory ...................................................................... 6 1.3 signal/pin descriptions .................................................................................................... .7 1.3.1 lpc interface ................................................................................................................. 7 1.3.2 inputs and outputs ...................................................................................................... .7 1.3.3 configuration straps and testing .................................................................................. 7 1.3.4 power and ground ........................................................................................................ 8 1.3.5 not connected ............................................................................................................ ... 8 1.4 internal pull-up and pull-down resistors .............................................................. 8 2.0 trusted platform module (tpm) overview 2.1 system connections . ................................ ................. ................................ ............. .......... .9 2.2 power management (pm) .................................................................................................... 9 2.3 host interface ............................................................................................................. ........ 9 3.0 i/o configuration registers 3.1 configuration register structure and access ............ ................ ............. ......... 10 3.1.1 the index-data register pair ...................................................................................... 10 3.1.2 tpm configuration records ........................................................................................ 10 3.1.3 reset configuration setup .......................................................................................... 11 3.1.4 register type abbreviations ....................................................................................... 11 4.0 tpm host interface 4.1 tpm interface module (tis) ............................................................................................ 12 4.1.1 features ................................................................................................................. ..... 12 4.1.2 host interrupt support ................................................................................................. 12 4.1.3 host tpm legacy interface registers ......................................................................... 12 5.0 device specifications 5.1 general dc electrical characteristics ................................................................. 13 5.1.1 recommended operating conditions ......................................................................... 13 5.1.2 absolute maximum ratings ......................................................................................... 13 5.1.3 capacitance ................................................................................................................ 13 5.1.4 power consumption under recommended operating conditions .............................. 14 5.2 dc characteristics of pins by i/o buff er types ......... ................. ................ ......... 15 5.2.1 input, ttl compatible ................................................................................................. 15 5.2.2 input, ttl compatible, with schmitt trigger ............................................................... 15 5.2.3 input, pci 3.3v compatible ......................................................................................... 15 5.2.4 output, ttl/cmos compatible, push-pull buffer ...................................................... 16 5.2.5 output, open drain buffer ........................................................................................... 16 5.2.6 output, pci 3.3v compatible ...................................................................................... 16 free datasheet http:// table of contents (continued) revision 1.1 5 www.nuvoton.com NPCT42X 5.2.7 notes and exceptions .................................................................................................. 17 5.3 internal resistors ......................................................................................................... .. 18 5.3.1 pull-up resistor ......................................................................................................... .. 19 5.3.2 pull-down resistor ...................................................................................................... 1 9 5.4 ac electrical characteristics .................................................................................... 20 5.4.1 ac test conditions ................................................................................................... 2 0 5.4.2 reset timing ............................................................................................................... 21 power-up reset ................................................................................................... 21 5.4.3 lpc interface timing ................................................................................................... 22 lclk and lreset ............... ................................ ....................................... ......... 22 lpc signals ............................................................................................................ 23 5.5 package thermal information ..................................................................................... 24 physical dimensions............................................................................................................ ............................. 25 free datasheet http:// www.nuvoton.com 6 revision 1.1 NPCT42X 1.0 signal/pin connecti on and description 1.1 connection diagram 1.2 buffer types and signal/pin directory the signal dc characteristics of the pins described in section 1.3 on page 7 are denoted by buffer type symbols, which are defined in table 1 . table 1. buffer types symbol description in t input, ttl compatible in ts input, ttl compatible, with 250 mv schmitt trigger in pci input, pci 3.3v compatible o p/n output, ttl/cmos compatible, push- pull buffer capable of sourcing p ma and sinking n ma od n output, ttl/cmos compatible, open- drain buffer capable of sinking n ma o pci output, pci 3.3v compatible pwr power pin gnd ground pin 28-pin thin shrink small outl ine package (tssop28), jedec order numbers: see back cover serirq lpcpd 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NPCT42X 28-pin tssop (top view) clkrun /gpio4 lad0 vss vdd lad1 lframe lclk lad2 vdd vss lad3 lreset 14 13 12 11 10 9 8 7 6 5 4 3 2 1 gpio1 gpio0/xor_out nc nc vss vsb gpio2/gpx pp test gpio3/badd nc nc nc nc nc = not connected free datasheet http:// 1.0 signal/pin connect ion and description (continued) revision 1.1 7 www.nuvoton.com NPCT42X 1.3 signal/pin descriptions this section describes all signals of the NPCT42X devices. the signals are organized by functional group. 1.3.1 lpc interface 1.3.2 inputs and outputs 1.3.3 configuration straps and testing signal pin(s) i/o buffer type power well description lad3-0 26, 23, 20, 17 i/o in pci /o pci v dd lpc address-data. multiplexed command, address bidirectional data and cycle status. lclk 21 i in pci v dd lpc clock. pci clock used for the lpc bus (up to 33 mhz). lframe 22 i in pci v dd lpc frame. low pulse indicates the beginning of a new lpc cycle or termination of a broken cycle. lreset 16 i in pci v dd lpc reset. pci system reset used for the lpc bus (hardware reset). serirq 27 i/o in pci /o pci v dd serial irq. the interrupt requests are serialized over a single pin, where each irq level is delivered during a designated time slot. clkrun 15 i/o d in pci /od 6 v dd clock run. indicates that lclk is going to be stopped and requests full-speed lclk (same behavior as pci clkrun ). lpcpd 28 i in pci v dd power down. indicates that power to the lpc interface is about to be turned off. when lpcpd functionality is not required, an internal pull-up resistor allows this pin to be left floating. signal pin(s) i/o buffer type power well description pp 7 i in ts v dd physical presence input. indicates owner?s physical presence. gpio4-0 15, 9, 6, 2, 1 i/o in ts /od 8 , o 4/8 v dd general-purpose i/o ports. general-purpose i/o pins compatible with the pc client tpm 1.2 specification . gpx 6 i/o in ts /od 8 v dd gpio-express-00. this pin may be configured as gpio- express-00 pin as described in the pc client tpm 1.2 specification . signal pin(s) i/o buffer type power well description test 8 i in ts v dd test mode enable. sampled at v dd power-up reset to force the device pins into a xor tree or tri-state ? configuration, as follows: ? no pull-up resistor (default) - normal device operation ? 4.7 k ? external pull-up resistor - pins configured for test mode. badd 9 i in ts v dd base address. sampled at v dd power-up reset to determine the base address of the configurat ion index-data register pair: ? no pull-down resistor (default) - 7eh-7fh ? 10 k ? external pull-down resistor - eeh-efh test mode selection. test mode (xor tree or tri-state) is selected by the sampled state of the badd pin during v dd power-up reset. when badd is sampled high, xor tree mode is selected. when badd is sampled low, tri-state mode is selected, floating all output pins. xor_out 1 o o 4/8 v dd xor tree output. this pin is the output of the xor tree test logic. free datasheet http:// 1.0 signal/pin connect ion and description (continued) www.nuvoton.com 8 revision 1.1 NPCT42X 1.3.4 power and ground 1.3.5 not connected 1.4 internal pull-up and pull-down resistors the signals listed in table 2 have internal pull-up (pu) and/or pull-down (pd) resistors. the internal resistors are optional for those signals indicated as ?programmable?. signal pin(s) i/o buffer type power well description vss 4, 18, 25 ignd ground. ground connection for both core logic and i/o buffers, for the main and standby power supplies. vdd 19, 24 i pwr main 3.3v power supply. powers the i/o buffers of the gpio ports and the lpc interface. vsb 5 i pwr standby 3.3v power supply. powers the on-chip core. signal pin(s) i/o buffer type power well description nc 3, 10-14 not connected. these pins may be either connected to any signal on the board or left unconnected. table 2. internal pull-up and pull-down resistors signal pin(s) power well type comments lpcpd 28 v dd pu 110 gpio4-0 15, 9, 6, 2, 1 v dd pu 110 programmable 1 1. default at reset: gpio0,2,3 enabled, gpio1,4 disabled. gpx 6 v dd pu 110 note 2 2. when gpio-express-00 (gpx) is selected for pin 6, the pull-up is enabled by default. pp 7 v dd pu 110 /pd 110 programmable 3 3. default at reset: pull-down enabled. test 8 v dd pd 110 strap free datasheet http:// 9 www.nuvoton.com revision 1.1 NPCT42X 2.0 trusted platform module (tpm) overview the NPCT42X devices provide tpm function ality in tcg 1.2-compliant systems and is designed to best meet the require- ments of pc systems. 2.1 system connections figure 1 shows the system connections of the NPCT42X in a typical pc application. tpm functions are all integrated on-chip. the major elements of the np ct42x interface are: host interface based on an lpc bus, with interrupt request. a physical presence input signal (pp) to indicate owner physical presence. gpio signals (gpio0-4), operated by tcg commands. 2.2 power management (pm) the NPCT42X devices have an advanced power management scheme. the wake-up scheme enables the NPCT42X to re- spond to any kind of event that may requir e its attention. power cons umption is minimized by dynamically adjusting the in- ternal power modes to the activity requir ed by the host commands and other operations. the security functions (core and asso ciated peripherals) are supplied by v sb , which must be connected to the system stand- by power source (must ex ist in acpi s3 state). 2.3 host interface the host bus interface is based on intel?s low pin count (lpc) interface, as defined in the lpc interface specification, revision 1.1 . this interface enables the host to perform read and write cycles using i/o space accesses as well as tpm accesses. the host interface works in ei ther legacy or tpm 1.2-compliant mode. figure 1. NPCT42X system connection diagram host system (lpc) lframe lad0-3 serirq lr eset lclk gpio NPCT42X lpcpd gpio clkrun 3.3v system main power 3.3v system standby power v dd v sb pp physical presence free datasheet http:// www.nuvoton.com 10 revision 1.1 NPCT42X 3.0 i/o configuration registers the NPCT42X host-controlled functions consist of a single logica l device (tpm interface), the host interface and a central set of configuration registers. the NPCT42X support two register mapping and configuration modes: legacy mode (as described throughout this document). this mode requires configuration, as described in the next section. tpm-lpc mode (see section 4.1 on page 12 and the tcg 1.2 pc client specific tpm interface specification ). this mode is self-contained and require s no additional configuration. the configuration and control register set supports acpi-compliant pnp confi guration, defined in appendix a of the plug and play isa specification, revision 1.0a by intel and microsoft. 3.1 configuration register structure and access the configuration register is access ed via the index-data register pair. 3.1.1 the index-data register pair access to the NPCT42X configuration regist ers is via an index-data register pair, using two system i/o byte locations. the base address of this register pair is determined during v dd power-up, according to the badd strap pin. table 3 shows the selected base addresses as a function of badd. table 3. badd strapping options the index register is an 8-bit read/write register located at the base address (base+0) . it is used as a pointer to the config- uration register structure and ho lds the index of the configurati on register that is currently accessible via the data register . the data register is an 8-bit register located at the base addr ess (base+1) used as a data path to any configuration register. accessing the data register actually acce sses the configuration regist er that is currently point ed by the index register. 3.1.2 tpm configuration records the NPCT42X tpm interface (tis) is associated with logical device number (ldn) 1ah. access to the registers in indexes 30h-71h is available only when the ldn register (index 07h) is set to 1ah. badd strap i/o address index register (base) data register (base + 1) high 7eh 7fh low eeh efh table 4. configuration register map index register name type reset comments 07h logical device number r/w 00h tpm is pnp ldn 1ah. 20h tpm device id (did) ro feh vendor-defined registers 27h tpm revision id (rid) ro - 30h logical device control (activate) r/w 00h 60h i/o base address descriptor 0 bits 15-8 r/w 00h 61h i/o base address descriptor 0 bits 7-0 r/w 00 h bits 3-0 (for a3-a0) are read only, ?0000?. 70h interrupt number and wake-up on irq enable r/w 00h 71h irq type select r/w 03h bit 1 is read/ write; other bits are read only. free datasheet http:// 3.0 i/o configuration registers (continued) revision 1.1 11 www.nuvoton.com NPCT42X 3.1.3 reset configuration setup the default configuration se tup of the NPCT42X is: the configuration base address is according to table 3 on page 10 . tpm logical device is disabled. the tpm interface is in legacy mode. all host configuration registers are set to their default values unless explicitly stated otherwise. 3.1.4 register type abbreviations the following abbreviations are used to indicate the register type: r/w= read/write. ro= read-only. write 0 to reserved bits unless another ?required value? is specified. this method can be used for registers containing bits of all types. free datasheet http:// www.nuvoton.com 12 revision 1.1 NPCT42X 4.0 tpm host interface this chapter describes the tp m 1.2-compliant host interface. 4.1 tpm interface module (tis) the tpm interface module implements a communication channel between the host and the tpm. the communication chan- nel is compatible with the tcg pc client specific tpm interface specification version 1.2 . the tpm interface module provides a mechanism for comm and and response transfers between the host and the NPCT42X. the host sends tpm commands via the tpm interface data fifo. the tpm executes the command and sends a response via the same data fifo. see the tpm main specification, version 1.2 for tpm command set definitions. 4.1.1 features access to tpm using dedicated lpc tpm transactions with locality levels 0 to 4. for details, see the tcg pc client specific tpm interface s pecification version 1.2 . legacy locality support using lpc i/o transactions. for details see section 4.1.3 . ? resource configuration via pnp configuration space. 4.1.2 host interrupt support the NPCT42X have one serirq interrupt to the host. when serir q is enabled, it can be set by any of the following events: locality change - whenever a new locality becomes active eit her because it seized control or because a previous lo- cality relinquished control; i.e. , this event is not set if no previous locality was active. command ready - on commandready bit transition from 0 to 1 (in tpm_sts register). status valid - on stsvalid bit transition from 0 to 1 (in tpm_sts register). data available - on dataavail bit transition from 0 to 1 (in tpm_sts register), if stsvalid bit is 1; or on stsvalid transition from 0 to 1, if dataavail bit is 1. 4.1.3 host tpm legacy interface registers the i/o base address is set via the i/o space configuration re gisters (index 60,61) of the tp m interface configuration regis- ters. table 5 shows the tpm legacy interface register mapping. all host tpm legacy interface registers correspond, in both name and structure, to the tp m interface registers defined in the tcg pc client specific tpm inte rface specification version 1.2 . note: addresses that do not appear in this table are not responded to by the tpm. table 5. host tpm legacy interface run-time registers tpm interface register offset in legacy lpc i/o address space comments tpm_int_enable 00h interrupt type is configured via index 71h. reserved bits and globalintenable bit are not implemented in the legacy address space. tpm_int_status 01h reserved bits 31-8 are not implemented in the legacy address space tpm_intf_capability 02h reserved bits 31-9 and burstcountstatic bit are not implemented in the legacy address space. tpm_sts(7-0) 03h tpm_sts(15-8) 04h burstcount (tpm_sts(24-16) are 0) tpm_data_fifo 05h free datasheet http:// revision 1.1 13 www.nuvoton.com NPCT42X 5.0 device specifications 5.1 general dc electrical characteristics 5.1.1 recommended operating conditions 5.1.2 absolute maximum ratings absolute maximum ratings are values beyond which damage to the device may occur. unless ot herwise specified, all volt- ages are relative to ground (v ss ). 5.1.3 capacitance symbol parameter min typ max unit v dd main 3v supply voltage 3.0 3.3 3.6 v v sb standby 3v supply voltage 3.0 3.3 3.6 v t a operating temperature 0 +70 ?c symbol parameter conditions min max unit v sup supply voltage 1 1. v sup is v dd , v sb . -0.3 +4.1 v v i input voltage -0.3 v dd + 0.5 v v o output voltage -0.3 v dd + 0.5 v t stg storage temperature -65 +165 ?c p d power dissipation 1w t l lead temperature soldering (10 s) +260 ?c esd tolerance c zap = 100 pf r zap = 1.5 k ? 2 2. value based on test complying with ra i-5-048-ra human body model esd testing. 2000 v symbol parameter conditions min typ 1 1. t a = 25 ? c; f = 1 mhz. max unit c in input pin capacitance 4 5 pf c inc lpc clock input capacitance lclk 5 8 12 pf c pci lpc pin capacitance lad3-0, lframe , lr eset , serirq, clkrun , lpcpd 810pf c io i/o pin capacitance 8 10 pf c o output pin capacitance 6 8 pf free datasheet http:// 5.0 device specifications (continued) www.nuvoton.com 14 revision 1.1 NPCT42X 5.1.4 power consumption under recommended operating conditions symbol parameter conditions 1 1. all parameters specified for 0 ? c ? t a ? 70 ? c; v dd and v sb = 3.3v ? 10% unless otherwise specified. typ max unit i dd v dd average supply current v il = 0.5v, v ih = 2.4v, no load 510ma i sb v sb average supply current v il = 0.5v, v ih = 2.4v, no load 20 50 ma i sblp v sb quiescent supply current in idle mode 2 2. device is not performing any operation; no lpc bus activity. v il = v ss , v ih = v sb , no load 300 700 ? a free datasheet http:// 5.0 device specifications (continued) revision 1.1 15 www.nuvoton.com NPCT42X 5.2 dc characteristics of pins by i/o buffer types the tables in this section summarize the dc char acteristics of all devi ce pins described in section 1.2 on page 6 . the char- acteristics describe the general i/o buffer types defined in table 1 on page 6 . the dc characteristics of the lpc interface meet the pci local bus specification (r ev 2.2 december 18, 1998) for 3.3v dc signaling. 5.2.1 input, ttl compatible symbol: in t 5.2.2 input, ttl compatible, with schmitt trigger symbol: in ts 5.2.3 input, pci 3.3v compatible symbol: in pci symbol parameter conditions min max unit v ih input high voltage 2.0 v sup 1 +0.5 1. v sup is v dd or v sb according to the power well of the input. v v il input low voltage ? 0.3 0.8 v i ilk 2 2. input leakage current includes the output leakage of the bidirectional bu ffers with tri-state outputs. for addi- tional conditions, see section 5.2.7 on page 17 . input leakage current v sup 3 = 3.0v - 3.6v and 0 < v in < v sup 3. v sup is v dd or v sb according to the power well of the input. ? 10 ? a v sup = 3.0v - 3.6v and v sup < v in ? 10 ? a symbol parameter conditions min max unit v ih input high voltage 2 v sup 1 +0.5 1. v sup is v dd or v sb according to the power well of the input. v v il input low voltage ? 0.3 0.8 v v h input hysteresis 300 mv i ilk 2 2. input leakage current includes the output leakage of the bidirectional bu ffers with tri-state outputs. for addi- tional conditions, see section 5.2.7 on page 17 . input leakage current v sup = 3.0v - 3.6v and 0 < v in < v sup ? 10 ? a v sup = 3.0v - 3.6v and v sup < v in ? 10 ? a symbol parameter conditions min max unit v ih input high voltage 0.5 v dd v dd +0.5 v v il input low voltage ? 0.3 0.3 v dd v i ilk 1 1. input leakage current includes the output leakage of the bidirectional bu ffers with tri-state outputs. for addi- tional conditions, see section 5.2.7 on page 17 . input leakage current v dd = 3.0v - 3.6v and 0 < v in < v dd ? 10 ? a v dd = 3.0v-3.6v and v dd 5.0 device specifications (continued) revision 1.1 17 www.nuvoton.com NPCT42X 5.2.7 notes and exceptions 1. i ilk and i olk are measured in the following cases (where applicable): ? internal pull-up or pull-down resistor is disabled ? push-pull output buffer is disabled (tri-state mode) ? open-drain output buffer is at high level 2. some pins have an internal static pull-up resistor (when enabled) and therefore ma y have leakage current from v sup (when v in = 0). see section 1.4 on page 8 for a list of the relevant pins. 3. some pins have an internal static pu ll-down resistor (when enabled) and ther efore may have leakage current to gnd (when v in = v sup ). see section 1.4 on page 8 for a list of the relevant pins. 4. the following strap pins have an internal static pull- up resistor enabled during power-up reset and therefore may have leakage current from v sb (when v in = 0): badd, test . 5. i oh is valid for a gpio pin only when it is not configured as open-drain. 6. in xor tree mode, the buffer type of the input pins included in the xor tree is in t (input, ttl compatible), regardless of the buffer type of these pins in normal device operation mode. free datasheet http:// 5.0 device specifications (continued) www.nuvoton.com 18 revision 1.1 NPCT42X 5.3 internal resistors dc test conditions notes : 1. v sup is v dd or v sb , according to the pin power well. 2. the equivalent resistance of the pull-up resistor is calculated by r pu = (v sup ? v pin ) / i pu . 3. the equivalent resistance of the pull-down resistor is calculated by r pd = v pin / i pd . device under te s t r pu pull-up resistor test circuit pull-down resistor test circuit v sup pin a i pu v v pin device under te s t r pd v sup pin a i pd v v pin v sup figure 2. internal resist or test conditions, t a = 0 ? c to 70 ?c, v sup = 3.3v device under te s t r pu internal pull-up strap internal pull-down strap v sup pin a i pu v v pin device under te s t r pd v sup pin a i pd v v pin v sup device under te s t r pu v sup pin a i pu v v pin device under te s t r pd v sup pin a i pd v v pin v sup (v pin < v il ) strap sampled ?high? v sup 10 k ? 10 ? a 10 ? a 10 ? a (v pin < v il )( v pin > v ih ) 10 ? a 10 k ? figure 3. internal resistor design requirements, t a = 0 ?c to 70 ? c, v sup = 3.3 v (v pin > v ih ) strap sampled ?low? strap sampled ?low? strap sampled ?high? free datasheet http:// 5.0 device specifications (continued) revision 1.1 19 www.nuvoton.com NPCT42X 5.3.1 pull-up resistor symbol: pu nn 5.3.2 pull-down resistor symbol: pd nn symbol parameter conditions 1 1. ta = 0 ? c to 70 ? c, v sup = 3.3v. min 2 2. not tested; guaranteed by characterization. typical max 2 unit r pu pull-up equivalent resistance v pin = 0v nn ?? 50% nn nn + 66% k ? symbol parameter conditions 1 1. ta = 0 ? c to 70 ? c, v sup = 3.3v. min 2 2. not tested; guaranteed by characterization. typical max 2 unit r pd pull-down equivalent resistance v pin = v sup nn ?? 50% nn nn + 120% k ? free datasheet http:// 5.0 device specifications (continued) www.nuvoton.com 20 revision 1.1 NPCT42X 5.4 ac electrical characteristics 5.4.1 ac test conditions figure 4. ac test conditions, t a = 0 ? c to 70 ?c, v sup = 3.0v - 3.6v notes : 1. v sup is v dd or v sb according to the power well of the pin. 2. c l = 50 pf for all output pins except the following pin gr oups (values include both jig and oscilloscope capacitance): s 1 = open ? for push-pull output pins. s 1 = v sup ? for high impedance to active low and active low to high-impedance transition measurements. s 1 = gnd ? for high impedance to active high and active high to high-impedance transition measurements. r l = 1.0 k ??? for all pins. 3. the following abbreviations are used in section 5.4 : re = rising edge; fe = falling edge definitions the timing specifications in this section are relative to v il or v ih (according to the specific buffer type) on the rising or falling edges of all the signals, as shown in the following figures (unless specifically stated otherwise). figure 5. input setup and hold time figure 6. clock-to-output and propagation delay device under te s t 0.1 ? f input output r l c l s 1 load circuit ac testing input, output waveform v sup v oh v ol v ih v il test points v ih v il (notes 1, 2, 3) t h clock input v ih v il v ih v il t su v ih v il input s etup time input h old time t val t oh clock or output v ih v il v ih v il v ih v il input output h old time output v alid time free datasheet http:// 5.0 device specifications (continued) revision 1.1 21 www.nuvoton.com NPCT42X 5.4.2 reset timing power-up reset symbol description reference conditions min 1 1. not tested; guaranteed by design. max t sb2dd v sb power-up to v dd power-up 0 ms t lrst1 v sb power-up to end of l reset lpc interface 100 ms t lrst l reset active time v dd power-up to end of lr eset 10 ms t plv strap valid time before end of l reset 10 ms straps t plv v dd (power) l reset v ddmin t lrst v sb (power) v sbmin t sb2dd t lrst1 free datasheet http:// 5.0 device specifications (continued) www.nuvoton.com 22 revision 1.1 NPCT42X 5.4.3 lpc interface timing the ac characteristics of the lpc interf ace meet the pci local bus specification (rev 2.2 december 18, 1998) for 3.3v dc signaling. lclk and lreset symbol parameter min max units t cyc 1 1. the lpc may have any clock frequency between nominal dc and 33 mhz. device operational parameters at frequencies under 16 mhz are guarant eed by design rather than by testing. the clock frequency may be changed at any time during the operation of the system as long as the clock edges remain ?clean? (mo notonic) and the mini mum cycle high and low times are not vio- lated. the clock may only be stopped in low state. lclk cycle time 30 ns t high lclk high time 2 2. not tested; guaranteed by characterization. 11 ns t low lclk low time 2 11 ns ? lclk slew rate 2,3 3. rise and fall times are specified in terms of the edge rate measured in v/ns. this slew rate must be met across the minimum peak-to-peak portion of the clock wavering (0.2 * v dd to 0.6 * v dd ) as shown below. 14v/ns ? lreset slew rate 2,4 4. the minimum lreset slew rate applies only to the rising (de-assertion) edge of the reset sig- nal and ensures that system noise cannot ma ke an otherwise monotonic signal appear to bounce in the switching range. 50 mv/ns t high t low t cyc 0.6 v dd 0.2 v dd 0.5 v dd 0.4 v dd 0.3 v dd 0.4 v dd p-to-p (minimum) v dd = 3.3v ? 10% free datasheet http:// 5.0 device specifications (continued) revision 1.1 23 www.nuvoton.com NPCT42X lpc signals symbol figure description ref erence conditions min max unit t val outputs output valid delay after re of clk 2 11 ns t on 1 1. not tested; guaranteed by characterization. outputs float to active delay after re of clk 2 ns t off 1 outputs active to float delay after re of clk 28 ns t su inputs input setup time before re of clk 7 ns t hl inputs input hold time after re of clk 0 ns t wlpd lpcpd asserted lpcpd active pulse width 2 t cyc leakage only leakage only 0.615 v dd 0.4 v dd 0.4 v dd lclk lad3 ? lad0, ldrq , serirq outputs t val t on t off v dd = 3.3v ? 10% t val lad3 ? lad0, serirq output enabled 0.285 v dd 0.4 v dd 0.4 v dd lclk lad3 ? lad0, lframe serirq inputs v dd = 3.3v ? 10% t hl t su lclk lpcpd t wlpd l pcpd asserted free datasheet http:// 5.0 device specifications (continued) www.nuvoton.com 24 revision 1.1 NPCT42X 5.5 package thermal information thermal resistance (degrees c/w) theta jc and theta ja values for the NPCT42X package are as follows: table 6. theta ( ? ) j values note: airflow for theta ja values is measured in linear feet per minute (lfpm). package type theta ja @0 lfpm theta ja @150 lfpm theta ja @250 lfpm theta ja @500 lfpm theta jc t s s o p 2 82 92 72 52 31 0 free datasheet http:// NPCT42X trusted pla tform module (tpm) www.nuvoton.com physical dimensions all dimensions are in millimeters. important notice nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, tr affic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. furthermore, nu- voton products are not intended for applications wherein failure of nuvoton products could result or lead to a situation wherei n personal injury, death or severe property or environmental damage could occur. nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indem nify nuvoton for any damages resulting from such improper use or sales. please note that all data and specificati ons are subject to change without notice. all trademarks of products and companies mentioned in this document belong to their respective owners. headquarters no. 4, creation rd. 3, science-based industrial park, hsinchu, taiwan, r.o.c tel: 886-3-5770066 fax: 886-3-5665577 http://www.nuvoton.com.tw (chinese) http://www.nuvoton.com (english) nuvoton technology corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-544-1718 fax: 1-408-544-1787 nuvoton technology (shanghai) ltd. 27f, 2299 yan an w. rd. shanghai, 200336 china tel: 86-21-62365999 fax: 86-21-62365998 taipei office 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c. tel: 886-2-2658-8066 fax: 886-2-8751-3579 winbond electronics corporation japan no. 2 ueno-bldg., 7-18, 3-chome shinyokohama kohoku-ku, yokohama, 222-0033 tel: 81-45-4781881 fax: 81-45-4781800 nuvoton technology (h.k.) ltd. unit 9-15, 22f, millennium city 2, 378 kwun tong rd., kowloon, hong kong tel: 852-27513100 fax: 852-27552064 for advanced pc product line information contact: apc.support@nuvoton.com ? ? 28-pin thin shrink small outl ine package (tssop28), jedec order numbers: NPCT42Xa: NPCT42Xaa0wx NPCT42Xb: NPCT42Xba0wx NPCT42Xc: NPCT42Xca0wx NPCT42Xd: NPCT42Xda0wx NPCT42Xl: NPCT42Xla0wx note: ?x? = ?0? or ?1? free datasheet http:// |
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